A semantic model for VHDL-AMS
نویسندگان
چکیده
This paper examines the analog extension to VHDL currently being discussed by the VHDL 1076.1 Working Group and proposes an underlying semantic model for it. The current white papers contain much discussion of syntactic and operational details and an abstraction away from that level of detail is presented here. This semantic model for VHDL-AMS extends our generally accepted semantics for VHDL (Breuer et al. 1995, Breuer & Mart́ınez Madrid 1995) in a natural way. It integrates the imperative, discrete-event semantics of VHDL and the declarative, continuous semantics of the AMS extension. The former is based on imperative pre-emptive scheduling primitives, and the latter is based on differential equations for varying real-valued quantities.
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